? semiconductor components industries, llc, 2013 june, 2013 ? rev. 0 1 publication order number: NCP340/d NCP340 soft-start controlled load switch the NCP340 is a low ron n ? channel mosfet controlled by a soft ? start sequence of 2 ms for mobile applications. the very low r ds(on) allows system supplying or battery charging up to dc 3a.the device is enable automatically if a power supply is connected on vin pin (active high) and maintained off if no vin (internal pull down). due to a current consumption optimization, leakage current is drastically decreased from the battery connected to the device, allowing long battery life. features ? 1.8 v ? 5.5 v operating range ? 30 m n ? mosfet ? dc current up to 3 a ? built ? in soft ? start 2 ms ? reverse voltage protection ? active high with integrated bridge ? compliance to iec61000 ? 4 ? 2 (level 4) 8.0 kv (contact) 15 kv (air) ? esd ratings: machine model = b human body model = 3 ? dfn4 1.2 x 1.6 mm ? this is a pb ? free device typical applications ? mobile phones ? tablets ? digital cameras ? gps ? computers in out en gnd NCP340 usb port gnd d+ d ? vbus vbat en in out cmic sbc charger system supply monitoring hs usb i c signal routing accessory detection and id 4 figure 1. typical application circuit tvs esd9x 1 f udfn4 case 517ce marking diagram http://onsemi.com see detailed ordering and shipping information on page 8 of this data sheet. ordering information 1 34 = specific device code m = date code 34 m (top view) in gnd out en pad1 pinout
NCP340 http://onsemi.com 2 pin function description pin name pin number type description in 1 power power ? switch input voltage; connect a 1 f or greater ceramic capacitor from in to gnd as close as possible to the ic. gnd 2 power ground connection; en 3 input enable input, logic high turns on power switch. out 4 output power ? switch output; connect a 1 f ceramic capacitor from out to gnd as close as pos- sible to the ic is recommended. pad1 power exposed pad can be connected to gnd plane for dissipation purpose or any other thermal plane. block diagram charge pump en block vref gate driver and soft start control in: pin1 en: 3 out: pin 4 2 battery figure 2. block diagram 1 f
NCP340 http://onsemi.com 3 maximum ratings rating symbol value unit in, out, en, pins: v en , v in , v out ? 0.3 to + 7.0 v from in to out pins: input/output v in , v out ? 7.0 to + 7.0 v esd withstand voltage (iec 61000 ? 4 ? 2) (note 1) (in and out when bypassed with 1.0 f capacitor minimum) esd iec 15 air, 8 contact kv human body model (hbm) esd rating are (notes 2 and 3) esd hbm 8000 v machine model (mm) esd rating are (notes 2 and 3) esd mm 250 v latch ? up protection (note 4) ? pins in, out, en lu 100 ma maximum junction temperature range t j ? 40 to + 125 c storage temperature range t stg ? 40 to + 150 c moisture sensitivity (note 5) msl level 1 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. guaranteed by design. 2. according to jedec standard jesd22 ? a108. 3. this device series contains esd protection and passes the following tests: human body model (hbm) 2.0 kv per jedec standard: jesd22 ? a114 for all pins. machine model (mm) 200 v per jedec standard: jesd22 ? a115 for all pins. 4. latch up current maximum rating: 100 ma per jedec standard: jesd78 class ii. 5. moisture sensitivity level (msl): 1 per ipc/jedec standard: j ? std ? 020. operating conditions symbol parameter conditions min typ max unit v in operational power supply 1.8 5.5 v v en enable voltage 0 5.5 t a ambient temperature range ? 40 25 + 85 c t j junction temperature range ? 40 25 + 125 c c in decoupling input capacitor 1 f c out decoupling output capacitor usb port per hub 1 f r ja thermal resistance junction to air udfn4 package (note 6) 170 c/w i out maximum dc current udfn4 package 3 a i peak maximum peak current 100 s pulse 15 a p d power dissipation rating (note 7) t a 25 c udfn4 package 0.58 w t a = 85 c udfn4 package 0.225 6. the r ja is dependent of the pcb heat dissipation. 7. the maximum power dissipation (p d ) is given by the following formula: p d t jmax t a r ja
NCP340 http://onsemi.com 4 electrical characteristics min & max limits apply for t a between ? 40 c to +85 c and t j up to + 125 c for vin between 1.8 v to 5.5 v (unless otherwise noted). typical values are referenced to t a = + 25 c and vin = 5 v. symbol parameter conditions min typ max unit power switch r ds(on) static drain ? source on ? state resistance v in = 3 v, v in = 5 v t j = 25 c 26 m ? 40 c < t j < 125 c 50 t r output rise time v in = 5 v c load = 1 f, r load = 125 (note 8) 0.5 2 4 ms t f output fall time v in = 5 v c load = 100 f, r load = 40 (note 8) 4 ms t on gate turn on v in = 5 v from vin applied to v out = 10% of fully on 0.5 2 4 ms v in = 3 v from vin applied to v out = 10% of fully on (note 9) 3 enable input en v ih high ? level input voltage 1.15 v v il low ? level input voltage 0.85 v r pd en pull ? down resistor 1 m r pu en pull ? up resistor 1.5 m reverse ? leakage protection i rev reverse ? current protection v in = 0 v, v out = 4.2 v (part disable), t j = 25 c 0.15 1 a quiescent current iq current consumption no load 100 200 a 8. parameters are guaranteed for c load and r load connected to the out pin with respect to the ground. 9. guaranteed by characterization.
NCP340 http://onsemi.com 5 typical characteristics figure 3. supply current vs. voltage figure 4. reverse current vs. output voltage v in , input voltage (v) v out , output voltage (v) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 0 20 40 60 80 100 120 140 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 figure 5. r ds(on) vs. v in voltage at 25 c figure 6. r ds(on) vs. v in voltage at 85 c v in , input voltage (v) v in , input voltage (v) 5.4 4.2 3.0 1.8 20 25 30 35 40 45 50 figure 7. r ds(on) vs. v in voltage at ? 40 c figure 8. r ds(on) vs. i out at 25 c i out , output current (a) i q , supply current ( a) i rev , reverse current ( a) r ds(on) (m ) 5.5 t a = ? 40 c t a = 25 c t a = 85 c 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 5.5 t a = ? 40 c t a = 25 c t a = 85 c i out = 0.5 a i out = 2 a i out = 1 a i out = 3 a 5.4 4.2 3.0 1.8 20 25 30 35 40 45 50 r ds(on) (m ) i out = 0.5 a i out = 2 a i out = 1 a i out = 3 a v in , input voltage (v) 5.4 4.2 3.0 1.8 20 25 30 35 40 45 50 r ds(on) (m ) i out = 0.5 a i out = 2 a i out = 1 a i out = 3 a 3.0 2.0 0.5 0 20 25 30 35 40 45 50 r ds(on) (m ) v in = 5.5 v 1.0 1.5 2.5 3.5 v in = 5.0 v v in = 3.0 v v in = 1.8 v
NCP340 http://onsemi.com 6 typical characteristics figure 9. r ds(on) vs. i out at 85 c figure 10. junction temperature vs. i out i out , output current (a) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 10 20 30 50 60 80 90 figure 11. logic threshold vs. v in figure 12. t on time on 75 ma load v in , input voltage (v) 6 5 4 3 2 1 0 0.94 0.95 0.96 0.97 0.98 0.99 1.01 1.02 figure 13. t off time on 75 ma load figure 14. t on time on 800 ma load t j , junction temperature ( c) en pin threshold (v) i out , output current (a) 3.0 2.0 0.5 0 20 25 30 35 40 45 50 r ds(on) (m ) 1.0 1.5 2.5 3.5 40 70 v in = 5.5 v v in = 5.0 v v in = 3.0 v 1.00 v ih vs. v in v il vs. v in
NCP340 http://onsemi.com 7 typical characteristics figure 15. t off time on 800 ma load figure 16. t on time on 2 a load figure 17. t off time on 2.3 a load
NCP340 http://onsemi.com 8 functional description overview the NCP340 is a high side n ? channel mosfet power distribution switch designed to connect external voltage directly to the system. the high side mosfet is automatically turned on if the vin voltage is applied thanks to internal pull up connected between vin and en pin. the turned off is obtained by vin removal. due to the soft start circuitry, NCP340 is able to limit large voltage surges. enable input enable pin is an active high. the part is off when vin is not present, limiting current consumption from battery to out pin. in the other side, the part is automatically turned on when v in is applied. blocking control the blocking control circuitry switches the bulk of the power nmos. when the part is off (no v in or en tied to gnd externally) , the body diode limits the leakage current i rev from out to in. in this mode, anode of the body diode is connected to in pin and cathode is connected to out pin. in operating condition, anode of the body diode is connected to out pin and cathode is connected to in pin preventing the discharge of the power supply. cin capacitor a in capacitor, 1 f, at least, capacitor must be placed as close as possible the part to be compliant with iec61000 ? 4 ? 2 (level 4). cout capacitor depending on the sinking current during system start up and system turn off, a capacitor must be placed on the output. a 1 f is strongly recommended but can be decreased down to 100 nf if the above two sequences are well controlled and parasitic inductance connected on the v out line is negligible. application information power dissipation the device?s junction temperature depends on different contributor factor such as board layout, ambient temperature, device environment, etc... yet, the main contributor in term of junction temperature is the power dissipation of the power mosfet. assuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: p d r ds(on) i out 2 p d = power dissipation (w) r ds(on) = power mosfet on resistance ( ) i out = output current (a) t j p d r ja t a t j = junction temperature ( c r ja = package thermal resistance ( c/w) t a = ambient temperature ( c) pcb recommendations the NCP340 integrates an up to 3 a rated nmos fet, and the pcb design rules must be respected to properly evacuate the heat out of the silicon. the dfn4 pad1 must be connected to ground plane to increase the heat transfer if necessary. by increasing pcb area, the r ja of the package can be decreased, allowing higher power dissipation . ordering information device marking package shipping ? NCP340mutbg 34 dfn4, 1.2x1.6 mm (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NCP340 http://onsemi.com 9 package dimensions udfn4 1.2x1.6, 0.5p case 517ce issue b notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.20 mm from the terminal tips. 4. package dimensions exclusive of burrs and mold flash. a b e d d2 e2 bottom view b e 4x note 3 2x 0.05 c pin one reference top view 2x 0.05 c a a1 (a3) 0.05 c 0.05 c c seating plane side view l 4x 1 2 dim min nom millimeters a 0.45 0.50 a1 0.00 ??? a3 0.13 ref b 0.25 0.30 d 1.20 bsc d2 0.76 0.86 e 1.60 bsc e2 0.40 0.50 e 0.50 bsc l 0.20 0.30 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. mounting footprint* detail b detail a 0.86 1.90 0.50 0.45 4x 0.50 dimensions: millimeters 0.25 4x recommended package outline l1 detail a l alternate terminal constructions l ??? ??? e/2 43 a m 0.05 b c pitch 1 0.55 0.05 0.35 0.96 0.60 0.40 0.15 max on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCP340/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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